Driver circuits that provide output clocking signals are utilized within integrated circuits. In particular, data processors have a need to control both a leading-edge and a back-edge characteristic of an output clocking signal that functions to enable circuits, transfer data, and latch data. Characteristics of an ideal output clocking signal include, but are not limited to: (1) fast leading-edge rise time; (2) fast back-edge fall time; and (3) no overlapping edges of separate output clocking signals. A fast leading-edge rise time is crucial for enabling time-critical circuits. A fast back-edge fall time and no overlapping edges of separate output clocking signals from separate driver circuits are critical in a data processing system to prevent a race condition.
A known method of providing controlled clock edge timing is with a boot-strap driver circuit. The boot-strap driver circuit works by isolating charge on a gate of a booting transistor, and an input clocking signal connected to a drain terminal of the booting transistor capacitively couples the trapped charge at the gate of the booting to a high voltage level. The high voltage on the gate allows the input clock signal, at the drain of the booting transistor, to be fully coupled to an output terminal of the boot-strap driver circuit without any voltage drop across the booting transistor. A problem with a bootstrap circuit is that an advanced semiconductor manufacturing process typically has thin gate oxides that can break down when a high voltage is applied.
Another known method of providing a controlled clocking signal within a data processor is with an inverter driven by a NAND-gate. The NAND-gate receives both an enable signal and a clock signal, and provides an output that drives an input to the inverter. An output of the inverter is the enabled clock signal. For example, a NAND-inverter combination is utilized within Motorola's commercially available 68HC000 microprocessor to generate core-driver signals and localized clocked enable signals. In systems using a plurality of clocked enabled NAND-inverter circuits, the clock edges of separate clocked enabled NAND-inverter combinations may have excessive overlapping. As mentioned above, the excessive overlapping of clock edges can lead to race conditions.
Therefore, within an integrated circuit which is required to avoid using any high-valued gate voltages (i.e. higher than the power supply voltage), controlled clocking signals that have ideal clock edge characteristics are required.